1. Field of the Invention
The present invention relates to an MIS (Metal-Insulator-Semiconductor) device, and particularly, to an MIS transistor. Specifically, the present invention relates to a thin film MIS-type semiconductor device formed on an insulating substrate, and more specifically, to a thin film transistor (TFT). In particular, the present invention relates to a MIS-type semiconductor device of a so-called reversed stagger type comprising a channel forming region on the upper side of a gate electrode. The present invention relates to a semiconductor integrated circuit formed on an insulating substrate, for example, an active matrix circuit and a driver circuit for image sensors.
2. Prior Art
Recently, devices comprising a thin film MIS-type semiconductor device formed on an insulating substrate are brought into practical use. Such a device can be found, for instance, in an active matrix-addressed liquid crystal device. Active matrix circuits commercially available at present include a type using a TFT and a type using a diode such as a MIM. In particular, the active matrix circuits of the former type are fabricated more actively because of the high quality image they yield.
Known active matrix circuits utilizing TFTs include those using polycrystalline semiconductors such as polycrystalline silicon and those using amorphous semiconductors such as amorphous silicon. A TFT using amorphous silicon is referred to hereinafter as an xe2x80x9camorphous silicon TFTxe2x80x9d. However, the TFTs of the former type cannot be applied to large area displays because of the process limitations. Accordingly, those of the latter type that are fabricated at a process temperature of 350xc2x0 C. or lower are mainly used for large area displays.
Referring to FIGS. 2 (A) to 2 (D), a process for fabricating a prior art amorphous silicon TFT of a reversed stagger type is described below. An alkali-free heat-resistant glass such as a Corning 7059 glass is used for the substrate 201. Since an amorphous silicon TFT is fabricated by a process with a maximum temperature of about 350xc2x0 C., materials well resistant to the maximum temperature must be used. In case of using the TFT in a liquid crystal panel, a material having a sufficiently high heat resistance and a high glass transition temperature must be employed to prevent thermal deformation from occurring on the substrate. From this context, Corning 7059 glass is suitable as a substrate material because it undergoes glass transition at a temperature slightly below 600xc2x0 C.
A TFT capable of stable operation can be realized by excluding mobile ions such as sodium ions from the substrate. The Corning 7059 glass contains very low alkali ions and is therefore ideal from this point of view. If a substrate containing considerable amount of an alkali ion such as sodium ion were to be used, a passivation film made from, for example, silicon nitride or aluminum oxide must be formed on the substrate to prevent mobile ions from intruding into the TFT.
After a coating is formed on the substrate using an electrically conductive material such as an aluminum or tantalum, a tantalum electrode 202 is formed by patterning using a mask 1. An oxide film 203 is formed on the surface of the gate electrode to prevent short circuit from occurring between the upper wiring and the gate electrode with wiring. The oxide film can be formed mainly by anodic oxidation. In such a case, the oxide film can be formed by applying a positive voltage to the electrode 202 in an electrolytic solution to oxidize the surface of the gate electrode.
A gate dielectric 204 is formed thereafter. In general, silicon nitride is used as the gate dielectric. However, the material for the gate dielectric is not only limited thereto, and it may be silicon oxide or a silicide containing nitrogen and oxygen at a desired ratio. The gate dielectric may be a film of single layer of a multilayered film. A plasma CVD process, for example, can be applied in case silicon nitride film is used as the gate dielectric. The plasma CVD process is effected at a temperature of about 350xc2x0 C., i.e., the maximum temperature of the present step. The structure thus obtained is shown in FIG. 2 (A).
An amorphous silicon film is formed thereafter. If the amorphous silicon film is deposited by plasma CVD, the substrate is heated to a temperature in the range of from 250 to 300xc2x0 C. The film is formed as thin as possible; specifically, it is formed generally at a thickness of from 10 to 100 nm, and preferably, in the range of from 10 to 30 nm. The amorphous silicon film is patterned using a mask {circle around (2)} to form an amorphous silicon region 205. The amorphous silicon region 205 thus formed provides the channel forming region in the later steps. The resulting structure is shown in FIG. 2 (B).
A silicon nitride film is formed on the entire surface of the resulting structure, and is patterned using a mask {circle around (3)} to provide an etching stopper 206. The etching stopper is provided to prevent accidental etching from occurring on the amorphous silicon region 205 in the channel forming region, because the amorphous silicon region 205 is provided thinly, as mentioned above, at a thickness of from 10 to 100 nm. Moreover, the etching stopper is designed in such a manner that it may be formed superposed on the gate electrode because the amorphous silicon region under the etching stopper functions as the channel forming region. However, misalignment occurs at some extent in the conventional mask alignment. Accordingly, the etching stopper is patterned in such a manner that it may be sufficiently superposed on the gate electrode (i.e., in such a manner that the etching stopper may be smaller than the gate electrode).
An N-type or P-type conductive silicon coating is formed thereafter. In general, an amorphous silicon TFT is of an N-channel type. Since the electric conductivity of an amorphous silicon film thus formed is insufficiently low in conductivity, a microcrystalline silicon film is used alternatively. An N-type conductive microcrystalline silicon film can be fabricated at a temperature of 350xc2x0 C. or lower by plasma CVD. Still, however, an N-type microcrystalline silicon film must be formed at a thickness of 200 nm or more because the resistance thereof is not sufficiently low. A P-type microcrystalline silicon film has an extremely high resistance and cannot be used as it is. Accordingly, it is difficult to fabricate a P-channel TFT from amorphous silicon.
The silicon film thus fabricated is patterned thereafter using a mask {circle around (4)} to provide an N-type microcrystalline silicon region 207. The resulting structure is shown in FIG. 2 (C).
The structure of FIG. 2 (C), however, cannot function as a TFT because the N-type microcrystalline silicon film is joined over the etching stopper. It is therefore necessary to separate the structure at the silicon film joint. Thus, the structure is separated using a mask {circle around (5)} to form a trench 208. If an etching stopper is not provided on the amorphous silicon layer, the base amorphous silicon layer may be accidentally damaged by the etching, because the microcrystalline silicon region 207 is several to several tens of times as thick as the underlying amorphous silicon region, or even thicker.
A wiring 209 and a pixel electrode 210 are formed thereafter by a known process using masks {circle around (6)} and {circle around (7)}. The state of the resulting structure is shown in FIG. 2 (D).
In the process above, however, the yield may be lowered because such a large number of masks amounting to 7 are used in the process. Thus, to decrease the number of masks, it is proposed to pattern the gate electrode portion using a first mask on the substrate. Then, a gate dielectric is formed to further deposit continuously thereon an amorphous silicon film and a silicon nitride film to later provide an etching stopper. The structure is exposed thereafter from the back to form an etching stopper in a self-aligned manner by selectively etching the silicon nitride film alone using the gate electrode portion as the mask. A TFT region inclusive of the trench on the upper portion of the channel (corresponding to the region 208 in FIG. 2) is formed using a second mask after forming a microcrystalline silicon film thereon. Then, a third and a fourth mask are used to form the wiring and the electrode. A structure equivalent to that shown in FIG. 2 (D) is finally obtained. It can be seen that a complete structure is obtained using less number of masks, i.e., 3 masks, by fully taking advantage of the self-aligned process.
As is seen in the figure, the TFT obtained above comprises irregularities. This is mainly due to the gate electrode portion (inclusive of the oxide 203 on the gate electrode), the etching stopper, and the microcrystalline silicon region. More specifically, for instance, a gate electrode portion having a thickness of 300 nm, an etching stopper 200 nm in thickness, and a microcrystalline silicon region 207 formed at a thickness of 300 nm in total yield an elevation as high as 800 nm in height on the substrate.
Considering a case the TFT is used as an active matrix circuit for a liquid crystal display panel, for example, the cell is generally about 5 to 6 xcexcm in thickness and is controlled within a precision of 0.1 xcexcm or less. Under such conditions, an irregularity as to reach a height of 1 xcexcm considerably impairs the uniformity of the cell thickness.
The factors affecting the thickness uniformity cannot be easily removed. For example, if the microcrystalline silicon film were to be formed thinly, the resistance of the source and drain is reversely increased to lower the device quality.
If a thin etching stopper were to be formed, on the other hand, the amorphous silicon region under the microcrystalline region may be accidentally etched during the etching process. If such an unfavorable etching should occur, the product yield may thereby be lowered.
The present invention has been accomplished in the light of the aforementioned circumstances. Accordingly, an object of the present invention is to simplify the process for manufacturing a semiconductor device. For instance, the number of masks is reduced to increase the yield. Otherwise, cost can be reduced by decreasing the number of film deposition steps to increase the throughput.
Another object of the present invention is to provide a semiconductor device such as a TFT having a further planarized surface. TFTs having a smooth surface not only resolve the problem in applying them to liquid crystal display panels, but also provides a solution to the key technical problems in other applications. Such TFTs with planarized structure allow them to be applied to novel application fields to which the prior art TFTs were not applicable.
A still other object of the present invention is to improve the TFT characteristics. The source/drain regions of the TFT shown in FIG. 2 yield a high sheet resistance which impairs the characteristics of the TFT. Moreover, the joint adhesiveness between the source/drain regions and the channel forming region is extremely poor because the source/drain regions are made from a material differing from that constituting the channel-forming region. It is also impossible to continuously form the source/drain regions after depositing the channel forming region. Thus, ideally, the joint adhesiveness between the source/drain regions and the channel forming region is improved by forming them from a single film within a same plane as in the MOS transistor of a semiconductor integrated circuit.
The aforementioned objects can be accomplished by a novel process for fabricating a TFT without using any etching stoppers, and by a TFT fabricated by the same process. More specifically, the resistance of the microcrystalline region (source/drain) is lowered sufficiently while increasing the thickness thereof. Furthermore, instead of a prior art two step process comprising forming an amorphous silicon region (film) for the channel forming region and a microcrystalline region (film) for the source/drain regions, the process according to the present invention comprises forming a single silicon film, and then separately forming the source/drain regions partly in the silicon film while forming the channel forming region in the other part thereof.
The throughput can be increased by solving the key problem of reducing the film deposition steps. The film deposition steps not only take time, but also consume considerable time which is equivalent to the time duration of the film deposition for cleaning inside the film deposition chamber. That is, a practical semiconductor process performed under an absolutely clean condition requires a long time to clean the chamber, and hence, the film deposition is effected during the spare time between the cleaning steps. It can be seen that an increase in throughput can be realized by forming thin coating instead of thick one, and by depositing a single layer coating instead of multilayered one. Thus, from the viewpoint of increasing the throughput, the film deposition steps are preferably reduced.
A TFT according to an embodiment of the present invention is an insulated gate transistor of reversed stagger type MIS TFT comprising a gate electrode coated with a gate dielectric and having thereon a semiconductor film, provided that the upper portion of the gate electrode is made from a substantially intrinsic semiconductor which provide a channel forming region. The other portions are either N-type or P-type conductive to provide source/drain regions having a structural degree of ordering higher than that of amorphous semiconductor of the channel forming region. The N-type or P-type semiconductor comprises a crystalline semiconductor which exhibits structural ordering as observed by a peak in Raman scattering spectra. The channel forming region may be amorphous, semi-amorphous, microcrystalline, polycrystalline, or may take an intermediate state between any two states enumerated above. The use of an amorphous semiconductor is preferred in case a suppressed OFF current is desirable. The regions which function as source and drain are made from crystalline silicon having a sufficiently low resistance. Furthermore, these regions are rendered crystalline and the crystal structure thereof is ameliorated by irradiating a laser light or an intense light equivalent thereto from 4 to 0.5 xcexcm in wavelength to the regions for a short period of time; the light specifically including an ultraviolet radiation, a visible light, and a near infrared radiation. These regions are rendered P-type or N-type by the irradiation of the ultraviolet radiation, the visible light or the near infrared radiation thereto according to the impurity introduced thereinto.
It can be seen that the structure above can be implemented by a single semiconductor film. Thus, the process above can be found suitable for mass production. Moreover, the surface irregularities of the TFT can be reduced because, unlike to the prior art processes, a thick microcrystalline silicon film is excluded from the process according to the present invention. As a matter of course, the process according to the present invention does not always require the impurity regions, for example, the channel forming region and the source/drain regions, be formed in a single semiconductor layer. Thus, those impurity regions may take a multilayered structure comprising two or more semiconductor layers to further improve the device characteristics while taking the cost and the performance into consideration. It should be noted, however, than in both cases, the source/drain regions as well as the channel forming region must be formed substantially in a single plane (layer).
A TFT according to another embodiment of the present invention is characterized in that no etching stopper is formed on the upper portion of the channel forming region. In this manner, the greatest factor for forming the surface irregularities can be eliminated from the TFT.